Microscale and nanoscale devices (hereinafter generically referred to as microscale devices) are important for a wide variety of applications. Such applications include increasingly high density semiconductor integrated circuits and a wide variety of electronic, optical, magnetic, mechanical, chemical and biological devices.
One important class of microscale devices comprises or is made from substrates having a major surface onto which a microscale pattern is formed. An exemplary such device comprises a substrate such as silicon having a surface (typically a major surface) with a polymeric resist coating that has been patterned, as by optical, electron, ion beam or imprint lithography, into a pattern that includes microscale features such as lines, holes, polygons or mesas that have one or more minimum lateral dimensions (parallel to the major surfaces) of less than ten micrometers. The patterning process typically involves forming a pattern in a polymeric resist coating. Sometimes, the resist pattern is then transferred onto the substrate as by etching and/or the deposition of materials. In such devices the performance may depend in major part on the small size, shape, and regularity of a microscale feature. For example, the speed and device density of an integrated circuit depends in large measure on the small size and regularity of the transistor gates, leads, and contact holes. And contemplated devices to manipulate, sort, and identify macromolecules and biological molecules such as DNA may need pathways comparable in width to the sub-10 nanometer transverse dimensions of the molecules.
However, there are limits on the fabrication of microscale devices by conventional techniques. In certain circumstances it is extremely difficult to accurately produce features having minimum dimensions of less than 10 nanometers, and it is difficult to make sub-20 nanometer patterns with high density. Furthermore, conventional fabrication techniques may produce defects such as line edge roughness (LER) and sloped side walls due to the statistical nature of each process and extrinsic limitations due to the fabrication environment (e.g., dust particles).
Applicant's U.S. Pat. No. 7,282,456 issued Oct. 16, 2007, describes a method for improving the shapes of microstructures after their initial fabrication. The shapes are improved by selectively liquefying (making flowable) the microstructures for a short period of time while applying a boundary plate to guide the flow of molten materials into the desired geometry before solidification. This process, referred to herein as self-perfection by liquefaction (SPEL), typically involves placing a flat plate above or in contact with the top surface of the nanostructure. It has been demonstrated that SPEL can significantly smooth line edge roughness, increase sidewall slope, and flatten and raise the top surface. For further details, see the aforementioned '456 patent, which is incorporated herein by reference. Nonetheless, there remain limitations on reducing the spacing between successive lines, the width of a trench, the spacing between mesas, the diameter of recessed holes, and the lateral dimensions of similar structures after their initial fabrication. The present invention provides additional post-lithography processing to reduce, adjust and improve the dimensions of such features.